1. Field of the Invention
The present invention relates to a CDMA (Code Division Multiple Access) code timing tracking in a CDMA type mobile communication system (i.e., a cellular communication system, a personal communication system or an IMT(International Mobile Telecommunication)-2000). More particularly, the present invention relates to a CDMA code timing tracking apparatus capable of exact code timing synchronization without regard to signal gain change by normalizing signal gain to synchronize code timing.
2. Description of the Related Art
In general, a CDMA (Code Division Multiple Access) is a method to enlarge frequency band of data signal with diffusion code, and then restores to original signal using the same diffusion signal. The CDMA method has several advantages that it is good for communication security and can effectively deal with multiple path signal attenuation.
In case of a CDMA type receiver, the receiver uses the same diffusion code as a transmitter and can restore to exact signal only when code phase of the received diffusion code and phase of diffusion code generated inside the receiver must correspond with each other.
As the algorithm for corresponding such code phase or timing synchronization, there are DLLs (Delay Locked Loops) using correlation value between early code, which is faster than on-time code, and late code, which is later than the on-time code, and TDLs (Tau-Dither Loops) using only one correlator.
Conventional synchronous DLLs, asynchronous DLLs, synchronous TDLs and asynchronous TDLs change speed for convergence of code phase synchronization according to the size change of signal.
FIG. 1 shows spreading code (PN Sequence) used for restoring CDMA code when the receiver of the conventional CDMA type mobile communication system applies the DLL.
Here, FIG. 1a shows on-time spreading code, FIG. 1b shows early code, which is /2 as fast as the on-time, and FIG. 1c shows late code which, is /2 as late as the on-time.
The on time means timing in the case of corresponding with the PN code phase of received signal.
The difference subtracting correlation value of the early code and received signal from correlation value of the late code and received signal is error signal being in proportion to code timing error.
The code timing synchronization using the DLL is to adjust the phase of spreading code to minimize error signal. The DLL is classified into two groups: one being a synchronous DLL performing in the state of restoring phase with carrier and the other being an asynchronous DLL performing without regard to phase restoration with carrier frequency.
FIG. 2 shows a structure of the synchronous DLL in the conventional CDMA type mobile communication system.
The synchronous DLL includes a PN code generator 11 for generating early code, which is faster than on-time code, and late code, which is later than the on-time code, a first correlator 12 for correlating the early code generated from the PN code generator 11 with baseband CDMA signal, which is input, a second correlator 13 the late code generated from the PN code generator 11 with the baseband CDMA signal, first and second low-pass filters for low-pass filtering signal output from the first and second correlators 12 and 13 respectively, a subtracter 16 for subtracting the output signal of the second low-pass filter 15 from output signal of the first low-pass filter 14 and generating difference signal, a third low-pass filter 17 for low-pass filtering the output signal of the subtracter 16, and a voltage-to-current converter 18 for converting voltage output from the third low-pass filter 17 into current and transmitting it to the PN code generator 11.
The synchronous DLL having the above structure generates early code, which is faster than on-time code, and late code, which is later than on-time code, and the first correlator 12 takes the correlation between the early code and the input baseband CDMA signal (r(t)).
Furthermore, the second correlator 13 takes the correlation between the late code generated from the PN code generator 11 and the baseband CDMA signal (r(t)). The first low-pass filter 14 low-pass filters output signal of the second correlator 13 and removes noise and high frequency element.
Next, the subtracter 16 subtracts the output signal of the second low-pas filter 15 from the output signal of the first low-pass filter 14 and generates difference signal, i.e., error signal in proportion to phase difference of spreading codes of the receiver and transmitter. The final role of the loop is to minimize error signal.
The output signal of the subtracter 16 is formularized as follows:                                           e            ⁡                          (              τ              )                                =                                                    p                ⁡                                  (                  τ                  )                                            ⁢                              R                ⁡                                  (                                      τ                    -                                                                  1                        2                                            ⁢                      Δ                                                        )                                                      -                          R              ⁡                              (                                  τ                  +                                                            1                      2                                        ⁢                    Δ                                                  )                                                    ,                            Formula        ⁢                  xe2x80x83                ⁢        1            
wherein p(xcfx84) is electric power of input signal, R(xcfx84xe2x88x92xc2xdxcex94) is the output signal of the first correlator 12, xcfx84 is chip timing error and xcex94 is phase difference between early spreading code and late spreading code of the receiver. Here, xcex94 uses the length of one chip.
The output signal of the subtracter 16 is low-pass filtered in the third low-pass filter 17, converted into current in the voltage-to-current converter 18 and transmitted to the PN code generator 11.
Here, when the size of the input signal is not uniform and changed by noise and multiple path, also the size of error signal is changed according to the change in the size of electric power P(xcfx84) of input signal. When error signal is changed, not only it has an influence on convergence time of the loop but also there is every probability that jitter is induced after the convergence.
FIG. 3 shows a structure of an embodiment of the asynchronous DLL in the conventional CDMA type mobile communication system.
The asynchronous DLL includes a PN code generator 20 for generating early code and late code, a first correlator 21 for correlating the early code generated from the PN code generator 20 with CDMA intermediate frequency signal which is input, a second correlator 22 for correlating the late code generated from the PN code generator 20 with the CDMA intermediate frequency signal, first and second band-pass filter 23 and 24 for band-pass filtering output signal of the first and second correlators 21 and 22 respectively, a first square unit 25 for squaring output signal of the first band-pass filter 23, a second square unit 26 for squaring output signal of the second band-pass filter 24, a subtracter 27 for subtracting output signal of the second square unit 26 from output signal of the first square unit 25 and generating difference signal, a low-pass filter 28 for low-pass filtering output signal of the subtracter 27, and a voltage-to-current converter 29 for converting voltage output from the low-pass filter 28 and transmitting it to the PN code generator 20.
The asynchronous DLL having the above structure generates early code, which is faster than on-time code, and late code, which is later than on-time code, in the PN code generator 20. The first correlator 21 takes the correlation between the early code and the CDMA intermediate frequency signal (r(t)).
Moreover, the second correlator 22 takes the correlation between the late code generated from the PN code generator 20 and the CDMA intermediate frequency signal (r(t)), the first band-pass filter 23 band-pass filters the output signal of the first correlator 21, and also the second band-pass filter 24 band-pass filters output signal of the second correlator 22.
Next, the first square unit 25 squares the output signal of the first band-pass filter 23, and the second square unit 26 squares the output signal of the second band-pass filter 24.
The subtracter 27 subtracts the output signal of the second multiplier 26 from the output signal of the first multiplier 25 and generates difference signal, i.e., baseband error signal. The final role of the loop is to minimize error signal.
The output signal of the subtracter 27 is formularized as follows:                                           e            ⁡                          (              τ              )                                =                                                                      p                  2                                ⁡                                  (                  τ                  )                                            ⁢                                                R                  2                                ⁡                                  (                                      τ                    -                                                                  1                        2                                            ⁢                      Δ                                                        )                                                      -                                          R                2                            ⁡                              (                                  τ                  +                                                            1                      2                                        ⁢                    Δ                                                  )                                                    ,                            Formula        ⁢                  xe2x80x83                ⁢        2            
wherein p2(xcfx84) is electric power of input signal, R2(xcfx84xe2x88x92xc2xdxcex94) is the output signal of the second square unit, R2(xcfx84+xc2xdxcex94) is the output signal of the first square unit, xcfx84 is chip timing error and xcex94 is phase difference between the early spreading code and the late spreading code of the receiver. Here, xcex94 uses the length of one chip.
As shown in FIG. 2, as the size of input signal is changed in electric power p(xcfx84) according to channel distortion or level change of signal, it has an influence on the converging effect of the asynchronous DLL.
Next, the output signal of the subtracter 27 is low-pass filtered in the low-pass filter 28, converted into current in the voltage-to-current converter 29 and transmitted to the PN code generator 20.
FIG. 4 shows a structure of another embodiment of the asynchronous DLL in the conventional CDMA type mobile communication system.
Differently from FIG. 3, in FIG. 4, baseband signal is input.
The asynchronous DLL includes a PN code generator 31 for generating early code and late code, a first correlator 32 for correlating the early code generated from the PN code generator 31 with baseband CDMA signal which is input, a second correlator 33 for correlating the late code generated from the PN code generator 31 with the input baseband CDMA signal, first and second low-pass filter 34 and 35 for low-pass filtering each output signal of the first and second correlators 32 and 33, a phase detector 40 for squaring each output signal of the first and second low-pass filters 34 and 35, subtracting the squared signal and generating error signal, a third low-pass filter 36 for low-pass filtering the output signal of the phase detector 40, and a voltage-to-current converter 37 for converting voltage output from the third low-pass filter 36 and transmitting it to the PN code generator 31.
The asynchronous DLL having the above structure generates early code, which is faster than on-time code, and late code, which is later than on-time code, in the PN code generator 31. The first correlator 32 takes the correlation between the early code and baseband CDMA signal (r(t)) which is input. Here, if the input signal is in QPSK (Quadriphase Phase Shift Keying) modulation, it may be divided into a real part element and an imaginary part element. Since the real part element and the imaginary part element pass the correlator at the same time, the first correlator 32 practically includes two multipliers, which output real part correlation value and imaginary part correlation value.
In the same way, also the second correlator 33 takes the correlation between the late code generated from the PN code generator 31 and the baseband CDMA signal (r(t)). If the input signal is in QPSK (Quadriphase Phase Shift Keying) modulation, it may be divided into a real part element and an imaginary part element. Since the real part element and the imaginary part element pass the correlator at the same time, the first correlator 32 practically includes two multipliers, which output real part correlation value and imaginary part correlation value.
The first low-pass filter 34 low-pass filters real part output signal and imaginary part output signal of the first correlator 32, and then transmits signal (E_re and E_im), from which noise and high frequency element are removed, to the phase detector 40.
Additionally, also the second low-pass filter 35 low-pass filters real part output signal and imaginary part output signal of the second correlator 33, and then transmits signal (L_re and L_im), from which noise and high frequency element are removed, to the phase detector 40.
The phase detector 40 squares four input signals respectively and adds by correlated signal. After that, the phase detector 40 subtracts obtained two signals and generates difference signal as error signal.
FIG. 5 shows an embodiment of the phase detector 40.
As shown in the drawing, the phase detector 40 includes first and second square units 41 and 42 for squaring real part output signal and imaginary part output signal of the first low-pass filter 34 respectively, third and fourth square units 43 and 44 for squaring real part output signal and imaginary part output signal of the second low-pass filter 35 respectively, a first adder 45 for adding output signal of the first and second square units 41 and 42, a second adder 46 for adding output signal of the third and fourth square units 43 and 44, and subtracter 47 for subtracting the output signal of the second adder 46 from the output signal of the first adder 45 and generating difference signal as error signal.
The phase detector 40 having the above structure squares real part output signal and imaginary part output signal output from the first low-pass filter 34 in the first and second square units 41 and 42 respectively. The first adder 45 adds the output signal of the first and second square units 41 and 42.
Furthermore, the third and fourth square units 43 and 44 square real part output signal and imaginary part output signal of the second low-pass filter 35 respectively. The second adder 46 adds the output signal of the third and fourth square units 43 and 44.
The subtracter 47 subtracts the output signal of the second adder 46 from the output signal of the first adder 45 and generates difference signal, i.e., error signal by the above formula 2.
Here, each of the square unit includes the multiplier inside.
Next, output signal of the phase detector 40 is low-pass filtered in the third low-pass filter 36, converted into current in the voltage-to-current converter 37 and transmitted to the PN code generator 31.
However, since the conventional asynchronous DLL for processing baseband signal uses a plurality of multipliers, each of which is more complex than the adder or the subtracter, there is problem that hardware implementation is complex.
It is, therefore, an object of the present invention to provide a CDMA (Code Division Multiple Access) code timing tracking apparatus capable of exact code timing synchronization without regard to signal gain change by normalizing signal gain to synchronize code timing.